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2kx8 dual-port static ram fax id: 5201 cy7c132/cy7c136 cy7c142/cy7c146 cypress semiconductor corporation ? 3901 north first street ? san jose ? ca 95134 ? 408-943-2600 december 1989 C revised march 27, 1997 1cy 7 c13 2/ cy7 c1 36 features ? true dual-ported memory cells which allow simulta- neous r eads of the same mem ory location ? 2k x 8 organization ? 0.65-micron cmos for optimum speed/power ? high-speed access: 15 ns ? low operating power: i cc = 90 ma (max.) ? fully asynchronous operation ? automatic power- down ? master cy7c132/cy7c136 easily expands data bus width to 16 or more bits using slave cy7c142/cy7c146 ? busy output flag on cy7c132/cy7c136; busy input on cy7c142/cy7c146 ? int flag for port-to-port communication (52-pin plcc/pqfp versions) ? available in 48-pin dip (cy7c132/142), 52-pin plcc and 52-pin tqfp (cy7c136/146) ? pin-compatible and functionally equivalent to idt7132/idt7142 functional description the cy7c132/cy7c136/cy7c142 and cy7c146 are high-speed cmos 2k by 8 dual-port static rams. two ports are provided to permit independent ac cess to any locat ion in memory. the cy7c132/ cy7c136 can be utilized as ei ther a standalone 8-bit dual-port static ram or as a master du- al-port ram in conjunction with the cy7c142/cy7c146 slave dual-port device in systems requiring 16-bit or greater word widths. it is the solution to applications requiring shared or buffered data such as cache memory for dsp, bit-slice, or multipro cessor designs. each port has independent cont rol pins; chip enable (ce ), write enable (r/w ), and output enable (oe ). busy flags are provided on each port. in addition, an interrupt flag (int ) is provided on each port of the 52-pin plcc version. busy sig- nals that the port is trying to access the same location currently being accessed by the other port. on the plcc version, int is an interrupt flag indicating that data has been placed in a unique location (7ff for the left port and 7fe for the right port). an automatic power-down feature is controlled independently on each port by the chip enable (ce ) pins. the cy7c132/cy7c142 are available in 48-pin dip. the cy7c136/cy7c146 are available in 52-pin plcc and pqfp. notes: 1. cy7c132/cy7c136 (master): busy is open drain output and requires pull-up resistor. cy7c142/cy7c146 (slave): busy is input. 2. open drain outputs; pull-up resistor required. logic block diagram pin configuration c132-1 c132-2 13 14 15 16 17 18 19 20 21 22 23 26 27 28 32 31 30 29 33 36 35 34 24 25 gnd r/w l busy l [1] ce l oe l a 10l a 0l a 0r a 10r r/w r ce r oe r ce r oe r ce l oe l r/w l r/w r i/o 7l i/o 0l i/o 7r i/o 0r busy r [1] int l [2] int r [2] arbitra tion logic (7c132/7c136 only) and interruptlogic (7c136/7c146 only) control i/o control i/o memory array address decoder address decoder 1 2 3 4 5 6 7 8 9 10 11 38 39 40 44 43 42 41 45 48 47 46 12 37 r/w l ce l busy l a 10l oe l a 0l a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l i/o 3l i/o 4l i/o 5l i/o 6l i/o 7l ce r r/w r busy r a 10r oe r a 0r a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r i/o 7r i/o 6r i/o 5r i/o 4r i/o 3r i/o 2r i/o 1r i/o 0r v cc dip top view 7c132 7c142
cy7c132/cy7c136 cy7c142/cy7c146 2 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ..................................... - 65 c to +150 c ambient temperature with power applied .................................................. - 55 c to +125 c supply voltage to ground potential (pin 48 to pin 24) .................................................- 0.5v to +7.0v dc voltage applied to outputs in high z state .....................................................- 0.5v to +7.0v dc input voltage .................................................- 3.5v to +7.0v output current into outputs (low) ............................. 20 ma static discharge voltage .......................................... >2001v (per mil-std-883, method 3015) latch-up current .................................................... >200 ma ] pin configurations (continued) 1 top view plcc oe r a 0r 8 9 10 11 12 13 14 15 16 17 18 19 20 46 45 44 43 42 41 40 39 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33 7 6 5 4 3 2 52 51 50 49 48 47 a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r nc i/o 7r a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l i/o 3l c132-3 7c136 7c146 46 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 1415 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 45 44 43 42 41 40 top view pqfp oe r a 0r a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r nc i/o 7r a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l i/o 3l c132-4 7c136 7c146 selection guide 7c136-15 [3,4] 7c146-15 7c132-25 [3] 7c136-25 7c142-25 7c146-25 7c132-30 7c136-30 7c142-30 7c146-30 7c132-35 7c136-35 7c142-35 7c146-35 7c132-45 7c136-45 7c142-45 7c146-45 7c132-55 7c136-55 7c142-55 7c146-55 maximum ac cess time (ns) 15 25 30 35 45 55 maximum operating current (ma) coml/ind 190 170 170 120 90 90 maximum operating current (ma) military 170 120 120 maximum standby current (ma) coml/ind 75 65 65 45 35 35 military 65 45 45 notes: 3. 15 and 25-ns version available in pqfp and plcc packages only. 4. shaded area contains preliminary information. operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% indust rial - 40 c to +85 c 5v 10% military [5] - 55 c to +125 c 5v 10% note: 5. t a is the instant on case temperature.
cy7c132/cy7c136 cy7c142/cy7c146 3 ] electrical characteristics over the operating range [6] parameter description test conditions 7c136-15 [3,4] 7c146-15 7c132-30 [3] 7c136-25,30 7c142-30 7c146-25,30 7c132-35 7c136-35 7c142-35 7c146-35 7c132-45,55 7c136-45,55 7c142-45,55 7c146-45,55 unit min. max. min. max. min. max. min. max. v oh output high voltage v cc = min., i oh = -4.0 ma 2.4 2.4 2.4 2.4 v v ol output low voltage i ol = 4.0 ma 0.4 0.4 0.4 0.4 v i ol = 16.0 ma [7] 0.5 0.5 0.5 0.5 v ih input high voltage 2.2 2.2 2.2 2.2 v v il input low voltage 0.8 0.8 0.8 0.8 v i ix input load current gnd < v i < v cc -5 +5 - 5 +5 - 5 +5 - 5 +5 m a i oz output leakage current gnd < v o < v cc , output disabled -5 +5 - 5 +5 - 5 +5 - 5 +5 m a i os output short circuit current [8] v cc = max., v out = gnd -350 - 350 - 350 - 350 ma i cc v cc operating supply current ce = v il , outputs open, f = f max [9] coml 190 170 120 90 ma mil 170 120 i sb1 standby current both ports, ttl inputs ce l and ce r > v ih , f = f max [9] coml 75 65 45 35 ma mil 65 45 i sb2 standby current one port, ttl inputs ce l or ce r > v ih , active port outputs open, f = f max [9] coml 135 115 90 75 ma mil 11 5 90 i sb3 standby current both ports, cmos inputs both ports ce l and ce r > v cc C 0.2v, v in > v cc C 0.2v or v in < 0.2v, f = 0 coml 15 15 15 15 ma mil 15 15 i sb4 standby current one port, cmos inputs one port ce l or ce r > v cc C 0.2v, v in > v cc C 0.2v or v in < 0.2v, active port outputs open, f = f max [9] coml 125 105 85 70 ma mil 105 85 capacitance [10] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 15 pf c out output capacitance 10 pf notes: 6. see the last page of this specification for group a subgroup testing information. 7. busy and int pins only. 8. duration of the short circuit should not exceed 30 seconds. 9. at f=f max , address and data inputs are cycling at the maximum frequency of read cycle of 1/t rc and using ac test waveforms input levels of gnd to 3v. 10. this parameter is guaranteed but not tested.
cy7c132/cy7c136 cy7c142/cy7c146 4 ] ac test loads and waveforms 3.0v 5v output r1893 w r2 347 w 30 pf including jigand scope gnd 90% 90% 10% <5ns <5 ns 5v output c132-5 r1893 w r2 347 w 5pf including jigand scope c132-6 (a) (b) output 1.4v equivalent to: th vnin equivalent 5v 281 w 30pf busy or int busyoutput load (cy7c132/cy7c136 only) 10% all input pulses 250 w switching characteristics over the operating range [6, 11] parameter description 7c136-15 [3,4] 7c146-15 7c132-25 [3] 7c136-25 7c142-25 7c146-25 7c132-30 7c136-30 7c142-30 7c146-30 unit min. max. min. max. min. max. read cycle t rc read cycle time 15 25 30 ns t aa address to data valid [12] 15 25 30 ns t oha data hold from address change 0 0 0 ns t ace ce low to data valid [12] 15 25 30 ns t doe oe low to data valid [12] 10 15 20 ns t lzoe oe low to low z [10, 13] 3 3 3 ns t hzoe oe high to high z [10, 13, 14] 10 15 15 ns t lzce ce low to low z [10, 13] 3 5 5 ns t hzce ce high to high z [10, 13, 14] 10 15 15 ns t pu ce low to power-up [10] 0 0 0 ns t pd ce high to power-down [10] 15 25 25 ns write cycle [15] t wc write cycle time 15 25 30 ns t sce ce low to write end 12 20 25 ns t aw address set-up to write end 12 20 25 ns t ha address hold f rom write end 2 2 2 ns t sa address set-up to write start 0 0 0 ns t pwe r/w pulse width 12 15 25 ns t sd data set-up to write end 10 15 15 ns t hd data hold from write end 0 0 0 ns t hzwe r/w low to high z [10] 10 15 15 ns t lzwe r/w high to low z [10] 0 0 0 ns
cy7c132/cy7c136 cy7c142/cy7c146 5 busy/interrupt timing t bla busy low from address match 15 20 20 ns t bha busy high from address mismatch [16] 15 20 20 ns t blc busy low from ce low 15 20 20 ns t bhc busy high from ce high [16] 15 20 20 ns t ps port set up for priority 5 5 5 ns t wb r/w low after busy low [17] 0 0 0 ns t wh r/w high after busy high 13 20 30 ns t bdd busy high to valid data 15 25 30 ns t ddd write data valid to read data valid note 18 note 18 note 18 ns t wdd write pulse to data delay note 18 note 18 note 18 ns interrupt timing [19] t wins r/w to interrupt set time 15 25 25 ns t eins ce to interrupt set time 15 25 25 ns t ins address to interrupt set time 15 25 25 ns t oinr oe to interrupt reset time [16] 15 25 25 ns t einr ce to interrupt reset time [16] 15 25 25 ns t inr address to interrupt reset time [16] 15 25 25 ns switching characteristics over the operating range [6, 11] (continued) parameter description 7c136-15 [3,4] 7c146-15 7c132-25 [3] 7c136-25 7c142-25 7c146-25 7c132-30 7c136-30 7c142-30 7c146-30 unit min. max. min. max. min. max. switching characteristics over the operating range [6, 11] 7c132-35 7c136-35 7c142-35 7c146-35 7c132-45 7c136-45 7c142-45 7c146-45 7c132-55 7c136-55 7c142-55 7c146-55 parameter description min. max. min. max. min. max. unit read cycle t rc read cycle time 35 45 55 ns t aa address to data valid [12] 35 45 55 ns t oha data hold from address change 0 0 0 ns t ace ce low to data valid [12] 35 45 55 ns t doe oe low to data valid [12] 20 25 25 ns t lzoe oe low to low z [10, 13] 333ns t hzoe oe high to high z [10, 13, 14] 20 20 25 ns t lzce ce low to low z [10, 13] 555ns t hzce ce high to high z [10, 13, 14] 20 20 25 ns t pu ce low to power-up [10] 000ns t pd ce high to power-down [10] 35 35 35 ns
cy7c132/cy7c136 cy7c142/cy7c146 6 write cycle [15] t wc write cycle time 35 45 55 ns t sce ce low to write end 30 35 40 ns t aw address set-up to write end 30 35 40 ns t ha address hold f rom write end 2 2 2 ns t sa address set-up to write start 0 0 0 ns t pwe r/w pulse width 25 30 30 ns t sd data set-up to write end 15 20 20 ns t hd data hold from write end 0 0 0 ns t hzwe r/w low to high z [10] 20 20 25 ns t lzwe r/w high to low z [10] 000ns busy/interrupt timing t bla busy low from address match 20 25 30 ns t bha busy high from address mismatch [16] 20 25 30 ns t blc busy low from ce low 20 25 30 ns t bhc busy high from ce high [16] 20 25 30 ns t ps port set up for priority 5 5 5 ns t wb r/w low after busy low [17] 000ns t wh r/w high after busy high 30 35 35 ns t bdd busy high to valid data 35 45 45 ns t ddd write data valid to read data valid note 18 note 18 note 18 ns t wdd write pulse to data delay note 18 note 18 note 18 ns interrupt timing [19] t wins r/w to interrupt set time 25 35 45 ns t eins ce to interrupt set time 25 35 45 ns t ins address to interrupt set time 25 35 45 ns t oinr oe to interrupt reset time [16] 25 35 45 ns t einr ce to interrupt reset time [16] 25 35 45 ns t inr address to interrupt reset time [16] 25 35 45 ns notes: 11. test co nditions assume signal transition ti mes of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3.0v and output loading of the specified i ol /i oh, and 30-pf load capacitance. 12. ac test conditions use v oh = 1.6v and v ol = 1.4v. 13. at any given temperature and voltage condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 14. t lzce , t lzwe , t hzoe , t lzoe, t hzce, and t hzwe are tested with c l = 5pf as in part (b) of ac test loads . transition is measured 500 mv from steady-state voltage. 15. the internal write time of the memory is def ined by the overlap of ce low and r/w low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input setup and hold timing should be referenced to the rising edge of the signal that terminat es the write. 16. these parameters are measured from the in put signal changing, until the output pin goes to a high-imped ance state. 17. cy7c142/cy7c146 only. 18. a write operation on port a, where port a has priority, leaves the data on port bs outputs undisturbed until one access tim e after one of the following: busy on port b goes high. port bs address toggled. ce for port b is toggled. r/w for port b is toggled during valid read. 19. 52-pin plcc and pqfp versions only. switching characteristics over the operating range [6, 11] (continued) 7c132-35 7c136-35 7c142-35 7c146-35 7c132-45 7c136-45 7c142-45 7c146-45 7c132-55 7c136-55 7c142-55 7c146-55
cy7c132/cy7c136 cy7c142/cy7c146 7 switching waveforms read cycle no. 1 (either port-address access) [20, 21] read cycle no. 2 (either port-ce /oe ) [20, 22] read cycle no. 3 (read with busy master: cy7c132 and cy7c136) n notes: 20. r/w is high for read cycle. 21. device is continuously selected, ce = v il and oe = v il . 22. address valid prior to or coincident with ce transition low. t rc t aa t oha data valid previous da ta valid data out address c132-7 t ace t lzoe t doe t hzoe t hzce data valid data out ce oe t lzce t pu i cc i sb t pd c132-8 t bha t bdd valid t ddd t wdd address match address match r/w r address r d inr address l busy l dout l c132-9 t ps t bla t rc t pwe valid
cy7c132/cy7c136 cy7c142/cy7c146 8 write cycle no.1 (oe three-states data i/os-either port) [15, 23] write cycle no. 2 (r/w threeCstates data i/os-either port) [15, 24] notes: 23. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or t hzwe + t sd to allow the data i/o pins to enter high impedance and for data to be placed on the bus for the required t sd . 24. if the ce low transition occurs simultaneously with or after the r/w low transition, the outputs remain in a high-impedance state. switching waveforms (continued) t aw t wc data valid high impedance t sce t sa t pwe t hd t sd t ha t hzoe ce r/w address oe d out data in c132-10 t aw t wc t sce t sa t pwe t hd t sd t hzwe t ha high impedance ce r/w address d out data in t lzwe data valid c132-11
cy7c132/cy7c136 cy7c142/cy7c146 9 busy timing diagram no. 1 (ce arbitration) busy timing diagram no. 2 (address arbitration) switching waveforms (continued) address match t ps ce l valid first: t blc t bhc address match t ps t blc t bhc ce r valid first: c132-12 c132-13 busy l ce r ce l address l,r busy r ce l ce r address l,r left addressvalid fi rst: address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r right address valid first: c132-14 c132-15
cy7c132/cy7c136 cy7c142/cy7c146 10 busy timing diagram no. 3 (write with busy , slave: cy7c142/cy7c146) interrupt timing diagrams [19] left side sets int r : right side clears int r : switching waveforms (continued) t pwe t wb t wh busy c132-16 r/w ce write 7ff t ins address l r/w l t wc t eins ce l t ha t sa t wins int r c132-17 read 7ff t rc t einr t ha t inr t oinr address r ce r r/w r int r oe r c132-18
cy7c132/cy7c136 cy7c142/cy7c146 11 right side sets int l : right side clears int l : interrupt timing diagrams [19] (continued) write 7fe t ins address r r/w r t wc t eins ce r t ha t sa t wins int l c132-19 read 7fe t einr t ha t inr t oinr address l ce l r/w l int l oe l t rc c132-20
cy7c132/cy7c136 cy7c142/cy7c146 12 typical dc and ac characteristics 1.4 1.0 0.4 4.0 4.5 5.0 5.5 6.0 -55 25 125 1.2 1.0 120 100 80 60 40 20 0 1.0 2.0 3.0 4.0 supplyvoltage(v) normalized supply current vs. supply voltage normalized supply current vs. ambient temperature ambienttemperature(c) outputvoltage(v) output source current vs. output voltage 0.0 0.8 0.8 0.6 0.6 v cc =5.0v v in =5.0v v cc =5.0v t a =25c 0 i cc i cc 1.6 1.4 1.2 1.0 0.8 -55 125 normalized access time vs. ambient temperature ambienttemperature(c) 1.4 1.3 1.2 1.0 0.9 4.0 4.5 5.0 5.5 6.0 supplyvoltage(v) normalized access time vs. supply voltage 120 140 100 60 40 20 0.0 1.0 2.0 3.0 4.0 0 80 outputvoltage(v) output sink current vs. output voltage v cc =5.0v t a =25c 0.6 0.8 v cc =5.0v t a =25c 1.25 1.0 0.75 10 40 0.50 normalized i cc vs. cycle time cycle frequency (mhz) 3.0 2.5 2.0 1.5 0.5 0 1.0 2.0 3.0 5.0 25.0 30.0 20.0 10.0 5.0 0 200 400 600 800 0 15.0 0.0 supplyvoltage(v) typical power- on current vs. supply voltage capacitance(pf) typical access time change vs. output loading 4.0 1000 1.0 20 30 0.2 0.6 1.2 i sb3 0.2 0.4 i sb3 25 1.1 v cc =4.5v t a =25c v cc =5.0v t a =25c v in =0.5v
cy7c132/cy7c136 cy7c142/cy7c146 13 shaded area contains preliminary information. ordering information speed (ns) ordering code package name package type operating range 30 cy7c132-30pc p25 48-lead (600-mil) molded dip commercial cy7c132-30pi p25 48-lead (600-mil) molded dip indust rial 35 cy7c132-35pc p25 48-lead (600-mil) molded dip commercial cy7c132-35pi p25 48-lead (600-mil) molded dip indust rial cy7c132-35dmb d26 48-lead (600-mil) sidebraze dip military 45 cy7c132-45pc p25 48-lead (600-mil) molded dip commercial cy7c132-45pi p25 48-lead (600-mil) molded dip indust rial cy7c132-45dmb d26 48-lead (600-mil) sidebraze dip military 55 cy7c132-55pc p25 48-lead (600-mil) molded dip commercial cy7c132-55pi p25 48-lead (600-mil) molded dip indust rial cy7c132-55dmb d26 48-lead (600-mil) sidebraze dip military speed (ns) ordering code package name package type operating range 15 cy7c136-15jc j69 52-lead plastic leaded chip carrier commercial cy7c136-15nc n52 52-pin plastic quad flatpack 25 cy7c136-25jc j69 52-lead plastic leaded chip carrier commercial cy7c136-25nc n52 52-pin plastic quad flatpack 30 CY7C136-30JC j69 52-lead plastic leaded chip carrier commercial cy7c136-30nc n52 52-pin plastic quad flatpack cy7c136-30ji j69 52-lead plastic leaded chip carrier industrial 35 cy7c136-35jc j69 52-lead plastic leaded chip carrier commercial cy7c136-35nc n52 52-pin plastic quad flatpack cy7c136-35ji j69 52-lead plastic leaded chip carrier industrial cy7c136-35lmb l69 52-square leadless chip carrier military 45 cy7c136-45jc j69 52-lead plastic leaded chip carrier commercial cy7c136-45nc n52 52-pin plastic quad flatpack cy7c136-45ji j69 52-lead plastic leaded chip carrier industrial cy7c136-45lmb l69 52-square leadless chip carrier military 55 cy7c136-55jc j69 52-lead plastic leaded chip carrier commercial cy7c136-55nc n52 52-pin plastic quad flatpack cy7c136-55ji j69 52-lead plastic leaded chip carrier industrial cy7c136-55lmb l69 52-square leadless chip carrier military
cy7c132/cy7c136 cy7c142/cy7c146 14 ordering information (continued) shaded area contains preliminary information. speed (ns) ordering code package name package type operating range 30 cy7c142-30pc p25 48-lead (600-mil) molded dip commercial cy7c142-30pi p25 48-lead (600-mil) molded dip indust rial 35 cy7c142-35pc p25 48-lead (600-mil) molded dip commercial cy7c142-35pi p25 48-lead (600-mil) molded dip indust rial cy7c142-35dmb d26 48-lead (600-mil) sidebraze dip military 45 cy7c142-45pc p25 48-lead (600-mil) molded dip commercial cy7c142-45pi p25 48-lead (600-mil) molded dip indust rial cy7c142-45dmb d26 48-lead (600-mil) sidebraze dip military 55 cy7c142-55pc p25 48-lead (600-mil) molded dip commercial cy7c142-55pi p25 48-lead (600-mil) molded dip indust rial cy7c142-55dmb d26 48-lead (600-mil) sidebraze dip military speed (ns) ordering code package name package type operating range 15 cy7c136-15jc j69 52-lead plastic leaded chip carrier commercial cy7c136-15nc n52 52-pin plastic quad flatpack 25 cy7c146-25jc j69 52-lead plastic leaded chip carrier commercial cy7c146-25nc n52 52-pin plastic quad flatpack 30 cy7c146-30jc j69 52-lead plastic leaded chip carrier commercial cy7c146-30nc n52 52-pin plastic quad flatpack cy7c146-30ji j69 52-lead plastic leaded chip carrier indust rial 35 cy7c146-35jc j69 52-lead plastic leaded chip carrier commercial cy7c146-35nc n52 52-pin plastic quad flatpack cy7c146-35ji j69 52-lead plastic leaded chip carrier indust rial cy7c146-35lmb l69 52-square leadless chip carrier military 45 cy7c146-45jc j69 52-lead plastic leaded chip carrier commercial cy7c146-45nc n52 52-pin plastic quad flatpack cy7c146-45ji j69 52-lead plastic leaded chip carrier indust rial cy7c146-45lmb l69 52-square leadless chip carrier military 55 cy7c146-55jc j69 52-lead plastic leaded chip carrier commercial cy7c146-55nc n52 52-pin plastic quad flatpack cy7c146-55ji j69 52-lead plastic leaded chip carrier indust rial cy7c146-55lmb l69 52-square leadless chip carrier military
cy7c132/cy7c136 cy7c142/cy7c146 15 military specifications group a subgroup testing dc characteristics switching characteristics parameter subgroups v oh 1, 2, 3 v ol 1, 2, 3 v ih 1, 2, 3 v il max. 1, 2, 3 i ix 1, 2, 3 i oz 1, 2, 3 i cc 1, 2, 3 i sb1 1, 2, 3 i sb2 1, 2, 3 i sb3 1, 2, 3 i sb4 1, 2, 3 parameter subgroups read cycle t rc 7, 8, 9, 10, 11 t aa 7, 8, 9, 10, 11 t ace 7, 8, 9, 10, 11 t doe 7, 8, 9, 10, 11 write cycle t wc 7, 8, 9, 10, 11 t sce 7, 8, 9, 10, 11 t aw 7, 8, 9, 10, 11 t ha 7, 8, 9, 10, 11 t sa 7, 8, 9, 10, 11 t pwe 7, 8, 9, 10, 11 t sd 7, 8, 9, 10, 11 t hd 7, 8, 9, 10, 11 busy/interrupt timing t bla 7, 8, 9, 10, 11 t bha 7, 8, 9, 10, 11 t blc 7, 8, 9, 10, 11 t bhc 7, 8, 9, 10, 11 t ps 7, 8, 9, 10, 11 t wins 7, 8, 9, 10, 11 t eins 7, 8, 9, 10, 11 t ins 7, 8, 9, 10, 11 t oinr 7, 8, 9, 10, 11 t einr 7, 8, 9, 10, 11 t inr 7, 8, 9, 10, 11 busy timing t wb [25] 7, 8, 9, 10, 11 t wh 7, 8, 9, 10, 11 t bdd 7, 8, 9, 10, 11 note: 25. cy7c142/cy7c146 only. document #: 38-00061-k
cy7c132/cy7c136 cy7c142/cy7c146 16 package diagrams 48-lead (600-mil) sidebraze dip d26 52-lead plastic leaded chip carrier j69
cy7c132/cy7c136 cy7c142/cy7c146 17 52-square leadless chip carrier l69 52-lead plastic quad flatpack n52 package diagrams (continued)
cy7c132/cy7c136 cy7c142/cy7c146 ? cypress s emiconduc tor corporation, 1997. the information contained herein is s ubject to change without notice. cypress semiconductor corporation assumes no re sponsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it c onvey or imply any license under patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconduc tor products in life-support sy stems application implies that the manufacturer assumes all risk of such use and in doing so indemni fies cypress semiconductor against all charges. 48-lead (600-mil) molded dip p25 package diagrams (continued)

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